CORERST=DISABLE, CLTO=OFF, ARBDIS=DISABLE, AUTOSN=DISABLE, TXBIL=EMPTY, GIBITO=DISABLE, SCLMONEN=DISABLE, GCAMEN=DISABLE, AUTOACK=DISABLE, SDAMONEN=DISABLE, BITO=OFF, SLAVE=DISABLE, CLHR=STANDARD, AUTOSE=DISABLE
No Description
| CORERST | Soft Reset the internal state registers 0 (DISABLE): No change to internal state registers 1 (ENABLE): Reset the internal state registers |
| SLAVE | Addressable as Follower 0 (DISABLE): All addresses will be responded to with a NACK 1 (ENABLE): Addresses matching the programmed follower address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. |
| AUTOACK | Automatic Acknowledge 0 (DISABLE): Software must give one ACK command for each ACK transmitted on the I2C bus. 1 (ENABLE): Addresses that are not automatically NACK’ed, and all data is automatically acknowledged. |
| AUTOSE | Automatic STOP when Empty 0 (DISABLE): A stop must be sent manually when no more data is to be transmitted. 1 (ENABLE): The leader automatically sends a STOP when no more data is available for transmission. |
| AUTOSN | Automatic STOP on NACK 0 (DISABLE): Stop is not automatically sent if a NACK is received from a follower. 1 (ENABLE): The leader automatically sends a STOP if a NACK is received from a follower. |
| ARBDIS | Arbitration Disable 0 (DISABLE): When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 1 (ENABLE): When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. |
| GCAMEN | General Call Address Match Enable 0 (DISABLE): General call address will be NACK’ed if it is not included by the follower address and address mask. 1 (ENABLE): When a general call address is received, a software response is required |
| TXBIL | TX Buffer Interrupt Level 0 (EMPTY): TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 1 (HALF_FULL): TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full |
| CLHR | Clock Low High Ratio 0 (STANDARD): Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 1 (ASYMMETRIC): Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 2 (FAST): Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 |
| BITO | Bus Idle Timeout 0 (OFF): Timeout disabled 1 (I2C40PCC): Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 2 (I2C80PCC): Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 3 (I2C160PCC): Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. |
| GIBITO | Go Idle on Bus Idle Timeout 0 (DISABLE): A bus idle timeout has no effect on the bus state. 1 (ENABLE): A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. |
| CLTO | Clock Low Timeout 0 (OFF): Timeout disabled 1 (I2C40PCC): Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 2 (I2C80PCC): Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 3 (I2C160PCC): Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 4 (I2C320PCC): Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 5 (I2C1024PCC): Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. |
| SCLMONEN | SCL Monitor Enable 0 (DISABLE): Disable SCL monitor 1 (ENABLE): Enable SCL monitor |
| SDAMONEN | SDA Monitor Enable 0 (DISABLE): Disable SDA Monitor 1 (ENABLE): Enable SDA Monitor |